The Code Morphing software system could
be a dynamic translation system, a program that compiles directions for x86 target instruction
set design (x86 ISA)
into directions for
VLIW host ISA at runtime. The Code Morphing software system resides during a read-only
storage and is that
the 1st program to start out corporal punishment once the processor boots.
It interprets a whole cluster of x86 directions quickly, making an optimized
translation, (whereas a superscalar x86 interprets single directions in isolation). Moreover, whereas a conventional x86 interprets every instruction each time it’s dead, on
a Crusoe, directions area unit translated once, and also the ensuing translation is
saved during a translation
cache, creating use
of Locality of
Reference property of code. Ensuing time
the (already translated) x86 code is dead, the system skips the interpretation step and directly executes the present optimized
translation. Not every bit of
code is translated within the same
manner: there’s a good selection of execution modes for x86 code, starting from interpretation
(which has no translation overhead in
the slightest degree, however
executes x86 code a lot of slowly),
through translation exploitation terribly simple-minded code
generation, all the thanks to extremely optimized code (which
takes longest to come up with, however that runs quickest once
translated). Dynamic feedback data gathered throughout actual execution of
the code optimizes this method.
Crusoe hardware, as compared with different x86 processors, can do glorious performance in dynamic translation, as a result of it’s been specifically designed
with dynamic translation in mind. The
flexibleness of the software-translation approach comes at a price:
the processor needs to dedicate a number of its cycles to running
the Code Morphing software; cycles that a traditional x86 processor may use to execute application code. However, the benefits of such an approach way outweigh its limitations.


It is a provision in TM5400 model Crusoe to reduce that processor is
already in lower power consumption. By quickly alternating
between running the processor at full speed and turning the processor off, most
typical x86 CPUs control their power consumption in a mobile setting. When a
time-critical application needs it, the processor may stop. In contrast, power
consumption can be adjusted in TM5400 without turning itself off- instead,
without even requiring an operating system reboot it can adjusts its clock
frequency on the fly. As a result, software can consistently observe the
requests on the processor and dynamically pick only the ideal clock speed (and
hence power utilization) supposed to run the application.

The importance of
the hybrid approach to microprocessor design is probably to become more obvious
over the next several years. The technology provides more scope to develop
(both hardware and software) than normal hardware-only outline. Nor is the
approach restricted to low-power designs or to x86-suited processors. Appliances like mobile computers and net access devices, laptop talents and unplugged running things of up to on
a daily basis are offered by Crusoe Processors.


The Crusoe microprocessor
is obtainable in the market in the subsequent variants: TM3120, TM3200, TM5400
and TM5600.The fundamental architecture of all the above models are same aside
from some minor changes since several models have been presented for several
sections of the mobile computing market. The subsequent architectural
explanation has taken Crusoe TM5400 as reference. The Crusoe Processor joins
number and drifting point execution units, isolate direction and information
stores, a level-2 compose back reserve, memory administration unit, and
interactive media guidelines. Additionally, these traditional processor
highlights, there are some further units, which are typically part of the core
system logic that encompasses the microprocessor. In mix with Code Morphing
programming and the extra framework core logic units, the VLIW processor,
permit the Crusoe Processor to produce a greatly incorporated, ultra-low power,
high performance stage results for the x86 mobile market.

Processor Core

The Crusoe Processor
core design is relatively easy by typical
standards. It’s upheld on a VLIW 128-bit
instruction set. At intervals this
VLIW design, the control
logic of the processor is kept basic and software is used to manage the planning
of instructions. This enables a
simplified and straightforward hardware implementation with an in-order
7-stage floating point pipeline
and a 10-stage floating-point pipeline. By streamlining the processor hardware
and reducing the control logic junction transistor count, the
performance-to-power consumption ratio relation are often greatly improved over
traditional x86 architectures.
Associate degree 8-way set associative Level one (L1) instruction cache, and a
16-way set associative L1 data cache are included in the Crusoe Processor. It
conjointly includes associate degree integrated Level two (L2) write cache for
improved effective memory information measure and increased performance. This
cache design assures most internal memory information measure for performance
intensive mobile applications, maintaining a similar low-power whereas
applications, implementation that has a superior performance-to-power consumption magnitude relation relative to previous x86

Other than having execution
h/w for logical, arithmetic, shift, and floating purpose
instructions, as in typical processors,
the Crusoe has terribly distinctive options
from ancient x86 styles. To ease the interpretation method from x86 to the core VLIW instruction
set, the h/w generates a similar condition
codes as typical x86
processors and operates on a
similar 80-bit floating-point numbers. Also, the TLB has the same
protection bits and address mapping as x86 processors. The s/w element of this solution is employed to emulate all alternative options of
the x86 design. The
software that converts x86 programs into the core VLIW directions is that the CMS.

Integrated DDR SDRAM Memory Controller

DDR SDRAM interface is that the highest performance
memory interface accessible on the Crusoe. The DDR SDRAM controller supports
only Double Data Rate(DDR)  SDRAM and
transfers data at a
rate that’s double the clock frequency of the
inter-face. This feature is absent within the model TM3200. The DDR SDRAM
controller supports up to 4 banks, the equivalent of 2 Dual In-line Memory
Modules(DIMMs) of DDR SDRAM employing a 64-bit wide interface. The DDR SDRAM
memory are often inhabited with 64M-bit, 128M-bit,
or 256M-bit devices. The frequency setting for the DDR SDRAM interface is
initialized throughout the
power-on boot sequence.

Integrated SDR SDRAM
Memory Controller

The SDR SDRAM memory
controller supports up to four banks, equal to
2 small Outline Dual In-line Memory Modules
(SO-DIMMS), of Single Data Rate
(SDR) SDRAM which will be designed as
64-bit or 72-bit SO-DIMMs. These SO-DIMMs can be inhabited with 64M-bit, 128M-bit or 256M-bit devices. All
SO-DIMMs should use a similar
frequency SDRAMs, however there aren’t any restrictions on mixing completely
different SODIMM configurations into every SO-DIMM slot. The frequency setting
for the SDR SDRAM interface is initialized throughout the power-on
boot sequence.

Integrated PCI Controller

The Crusoe Processor
includes a PCI bus controller that’s PCI 2.1 compliant. The
 PCI bus
is thirty two bits
wide, operates at thirty three MHz, and is compatible with 3.3V signal level. It’s not 5V
tolerant, however. The PCI controller on provides a PCI host bridge the PCI bus
arbiter, and a DMA controller.
Serial ROM Interface

Crusoe serial ROM interface could be a five-pin
interface used to browse data from
a serial flash ROM.
The flash ROM is 1M-byte in
size and provides non-volatile
memory for the CMS. Throughout the
boot method, the Code
Morphing code is traced from
the ROM to the Code Morphing memory area in SDRAM. The Code Morphing code needs eight to 16M-bytes of memory area once it is moved. The part of SDRAM space kept for CMS is invisible to x86 code.
Transmeta provides programming
information for the flash ROM.
This interface may be
used for in-system reprogramming of the flash ROM.


Basic principles of VLIW Architecture

VLIW stands for Very Long Instruction Word.
VLIW may be a methodology that mixes multiple customary directions into one long instruction word. This word contains
instruction which will be executed at identical time on separate chips
or completely different components of identical chip. It provides
explicit parallelism i.e. executing
more than one basic (primitive) instruction at a time. By using VLIW
we modify the compiler, not the chip to
determine that instructions are often run at the same time. This is often a
bonus as a result of the compiler is aware of a lot of information concerning
the program than the chip will by the time the code gets to  chip.
Trace scheduling is a
vital technique in VLIW process i.e. the compiler processes the code and
determine that path is the most often traveled, and so optimizes this path.
Basic blocks that compose the path are separated from the opposite basic block. The path
is then optimized and rejoined with the other basic blocks using split and
rejoin blocks.

Dynamic scheduling is
another vital methodology once assembling VLIW code. The procedure alluded to
as split-issue parts the code into 2 stages, stage 1 and 2. This considers
numerous instructions, instructions having bound postponements and so forth to
execute in the meantime.  Hardware
support is required to execute this, and requires defer cushions and transitory
variable space (TVS) inside the hardware. The TVS is required to store results when they are available in. The
results computed in phase 2 are held in temporary variables and loaded into the suitable phase
1 register when they are required.

VLIW has been explained as a natural successor to
RISC whose instruction set consists of simple instructions (RISC-like). As a result of it moves complexity from the hardware to
the compiler, permitting less complicated, quicker processors. One objective of
VLIW is to eliminate the sophisticated instruction planning. The compiler should assemble many primitive
operations into one “instruction word” specified the multiple functional
units are kept busy.                                                      

Crusoe VLIW in

With the Code Morphing software package handling x86
compatibility, Transmeta
hardware designers created a simple, superior, VLIW engine with 2
integer units, a floating-point unit, a memory
(load/store) unit, and a branch unit A Crusoe processor long instruction
word, referred to as a
molecule, could also be sixty
four bits or 128 bits long and is referred
to as atoms which contain up to four RISC-like instructions. There
is no mind complex out-of-arrange equipment since molecules are executed all
together. To remain the processor running at full


speed, molecules are packed
as completely as conceivable with atoms. The integer register file has sixty
four registers, %r0 through %r63. By tradition, the Code Morphing programming
bundle designates some of these to convey x86 state while others contain state
inside to the framework, or might be utilized as impermanent registers, e.g.,
for enroll renaming in software package Superscalar out-of-arrange x86 processors, for example,
the Pentium II and III processors, additionally have different functional units
that can execute RISC-like operations (micro-ops) in parallel. A different bit
of hardware, is required since the dispatch unit reorders the the micro-ops as
expected to keep the functional units occupied. To effectively reconstruct the
order of the first x86 instructions, and make sure that they go in correct order. Clearly, this sort of processor
hardware is way a lot of complicated than the Crusoe
processor’s simple VLIW
engine. The decoding and
dispatching hardware needs giant quantities of power-hungry
logic transistors, since the x86 instruction set is kind of complicated
and the chip dissipates heat in rough proportion to their numbers


The Crusoe processor
provides x86-compatible software execution while not requiring code
recompilation when employed in conjunction with Transmeta’s x86 Code
Morphing software package,.
Systems supported this  solutions are  capable of executing all normal x86-compatible operative systems and
applications, together with Microsoft
Windows 9x,
Windows ME, Windows 2000, and Linux.



In mobile computing, in
which complex power hungry processors have constrained

clients to surrender either
battery running time or execution. The Crusoe processor

arrangements have been
intended for lightweight (two to four pound) portable PCs

what’s more, Internet get to
gadgets, for example, handhelds and web cushions. They can give these gadgets
PC abilities and unplugged running circumstances of up to a day.Crusoe
processor chips redesigned using the basics of microprocessor chip
design. Pick an imaginative approach that
utilizes a special blend of hardware and software. Utilizing software  to deteriorate complex instructions into
simple atoms and to plan and optimize the atoms for parallel execution spares a
great many logic transistors and cuts power utilization.

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